1. Field of the Invention
The present invention relates to a structure of a voltage generating circuit responsive to a reference voltage for outputting a negative voltage and, particularly to a structure of a voltage generating circuit with high control responsiveness for a voltage while ensuring an operation reliability of a transistor in the voltage generating circuit. The present invention also relates to a semiconductor memory device using the voltage generating circuit for driving a word line.
2. Description of the Background Art
Recently, an instrument driven by a battery such as a portable personal computer or information terminal instrument is widely used. Thus, reduction in power consumption of a semiconductor memory, that is, at a low voltage operation, is required.
A size of a transistor is on the decrease due to development in fine patterning of the transistor with increase in a capacity of a semiconductor memory. In this respect, the low voltage operation is an indispensable requirement to ensure a reliability of the operation of the transistor.
In this context, a relation between an operating voltage (Vcc) and a threshold voltage (Vt) of the transistor is becoming important. Generally, an operation speed of a transistor is in inverse proportion to a difference between a power supply voltage and a threshold voltage, that is, Vccxe2x88x92Vt. Thus, threshold voltage Vt must be decreased to ensure a sufficient speed with the low voltage operation.
However, as threshold voltage Vt decreases, a subthreshold current in a cut-off region increases. In a dynamic random access memory (which is hereinafter abbreviated as DRAM) which is used as a general-purpose product, data holding time is preliminary defined as a specification. The aforementioned problem has a significant impact on a transistor especially used for a memory cell of a DRAM. More specifically, increase in a leakage current results in reduction in the data holding time, and therefore it is extremely difficult to allow threshold voltage (Vt) to be freely decreased with decrease in operating voltage (Vcc).
For sufficiently writing data at an xe2x80x9cHxe2x80x9d level to a memory cell, a maximum word line voltage corresponding to a selection state (xe2x80x9cHxe2x80x9d level) of the word line which is connected to a gate of an access transistor of the memory cell must be set at Vcc+Vt or higher. Thus, threshold voltage (Vt) must be set at a low value in order to ensure a reliability of the gate oxide film of a fine patterned transistor.
As described above, setting of threshold voltage (Vt) of the transistor is extremely difficult with such requirement for the low voltage operation of the semiconductor memory.
To solve this problem, a structure of a word line which is driven by a negative voltage has been proposed as shown in xe2x80x9cLow Voltage Circuit Design Techniques for Battery-Operated and/or Giga-Scale DRAM""sxe2x80x9d, by T. Yamagata et al., IEEE Journal of Solid-State Circuits. 1995, pp. 1183-1188 (which is hereinafter called as a first conventional art).
In the first conventional art, a maximum word line voltage (that is a voltage applied to a gate of a transistor of a memory cell) required for writing data at the xe2x80x9cHxe2x80x9d level is decreased by decreasing a threshold voltage of the transistor of the memory cell, so that reliability of the transistor is ensured. At the same time, a negative voltage is applied to the word line when holding data to prevent leakage of a subthreshold voltage, so that a sufficient data holding time is ensured.
To implement the structure, stability of the negative voltage applied to the word line when holding data is very important. The subthreshold current causing leakage increases by about ten times if a gate voltage increases by 0.1V. Thus, a voltage generating circuit capable of supplying a negative voltage with high accuracy is required for driving the word line.
A structure has been proposed as a negative voltage generating circuit with accuracy which can be used for this purpose in xe2x80x9cA Precise On-Chip. Voltage Generator for a Giga-Scale DRAM with a Negative Word-Line Schemexe2x80x9d, by H. Tanaka et al., 1998 Symposium on VLSI Circuits Digest of Technical Papers, pp. 94-95 (which is hereinafter called as a second conventional art).
FIG. 9 is a schematic block diagram showing an overall structure of a voltage generating circuit 500 of the second conventional art.
Referring to FIG. 9, voltage generating circuit 500 includes: a charge pump regulator 530 outputting a negative voltage Vbb to a line 532; a differential amplifier 510 comparing a reference voltage Vrn and an output voltage Vnn and amplifying a difference therebetween for output; and an N channel transistor 520 responsive to an output from differential amplifier 510 for controlling an amount of electric charges supplied for a line 533 transmitting output voltage Vnn from the line 532.
Voltage generating circuit 500 is applied to a semiconductor memory device, and generates output voltage Vnn(xe2x88x920.75V) used for driving a word line when holding data and Vbb(xe2x88x921.0V) used as a voltage for back bias of a semiconductor substrate.
An exemplary circuit structure of charge pump regulator 530 is shown, for example, in Ultra LSI Memory (by Kiyoo Ito, Baifukan) pp. 241-242. FIG. 10 is a circuit diagram showing an exemplary structure of charge pump regulator 530.
Referring to FIG. 10, charge pump regulator 530 includes a self-oscillator 540 and a charge pump circuit 550. Self-oscillator 540 generates a pulse signal at a frequency f1 with two states of xe2x80x9cHxe2x80x9d level (cc) and xe2x80x9cLxe2x80x9d level (GND).
Charge pump circuit 550 includes: an output node Ne; an intermediate node Nb; a charge capacitor C1 receiving an output from self-oscillator 540 and connected to intermediate node Nd; a transistor Q1 for rectification connected between intermediate node Nd and a ground line; and a transistor Q2 for rectification connected between intermediate node Nd and output node Ne. There is a parasitic capacitance C2 (C1 greater than  greater than C2) between intermediate node Nd and the ground line.
Voltage Vbb generated at output node Ne is applied to a substrate (a substrate capacitance CSUB) as a back bias voltage. Consumed substrate current is indicated by a current source (Ibb) connected in parallel to substrate capacitance CSUB.
In charge pump circuit 550, a voltage in pulse (with amplitude of Vcc) is periodically applied to the capacitance of charge capacitor C1, and transistor Q1 or transistor Q2 is turned on in accordance with a potential at intermediate node Nd. Thus, electrons stored in charge capacitor C1 are supplied for a load (substrate capacitance CSUB) until output voltage Vbb at node Ne reaches a maximum negative voltage Vnmin=xe2x88x92Vcc+Vt1+Vt2(Vt1: threshold voltage of transistor Q1, Vt2: threshold voltage of transistor Q2).
Conversely, when back bias voltage Vbb is externally applied, a current supplying ability of charge pump regulator 530 is represented by a product of xcex94V(xcex94V=Vbbxe2x88x92Vnmin), which is a difference between the above mentioned maximum negative voltage Vnmin and output voltage Vbb, a capacitance value of the charge capacitor and frequency f of the self-oscillator (C1xc2x7xcex94Vxc2x7f).
Body regions of transistors Q1 and Q2 included in charge pump circuit 550 are connected to output node Ne, and transistors Q1 and Q2 are also back biased by output voltage Vbb. Thus, a voltage at Vccxe2x88x92Vbb at maximum is applied to a gate oxide film of transistor Q1.
Voltage generating circuit 500 maintains output voltage Vnn at reference voltage Vrn by driving differential amplifier 510 by voltage Vbb at an output node of charge pump regulator 530 and a power supply voltage Vcc, controlling an amount of current through a current path formed in transistor 520 in accordance with an output from differential amplifier 510 and supplying electric charges necessary for the line 533. Voltage generating circuit 500 is characterized in that, even when voltage Vbb changes, the affect of the change is not readily transmitted to output voltage Vnn.
In voltage generating circuit 500, however, supply of electric charges for controlling output voltage Vnn is performed through a transistor 520, so that an ability of supplying electric charges of the transistor is extremely low when a source-drain voltage Vds applied to transistor 520 is small. In the second conventional art, Vds is as low as 0.25V as output voltage Vnn=xe2x88x920.75V and substrate voltage Vbb=xe2x88x921.0V, and therefore it is difficult to ensure sufficient responsiveness of output voltage Vnn.
When the source-drain voltage of transistor 520 is to be ensured by decreasing output voltage Vbb of charge pump regulator 530 in order to increase responsiveness of output voltage Vnn, a maximum value of the voltage applied to the gate oxide film of transistor Q1 shown in FIG. 10 increases. Thus, reliability of the transistor is reduced because of the relation with the size of the transistor forming the charge pump circuit.
The ability of supplying electric charges of charge pump circuit 550 is determined depending on the relation between maximum negative voltage Vnmax and output voltage Vbb or the like, as described above. When current consumption for the word line exceeds the supplying ability of charge pump circuit 550, both of voltages Vnn and Vbb would ultimately change in a positive direction.
FIG. 11 is a schematic diagram shown in conjunction with changes in voltages Vnn and Vbb with an operation of the word line.
Referring to FIG. 11, when a large amount of current is consumed by an operation of the word line, a significant amount of electric charges is supplied form the line 532 supplying Vbb. In this case, for the second conventional art, charge pump regulator 530 which inherently performs power supply for back bias of the substrate further supplies current necessary for driving the word line during data holding time. As a result, the voltage may disadvantageously be changed in the positive direction.
An object of the present invention is to provide a voltage generating circuit including a transistor with a thin gate oxide film designed for an operation at a low voltage and capable of generating a negative voltage having a sufficient control responsiveness while ensuring an operation reliability of the transistor.
Another object of the present invention is to provide a structure of a semiconductor memory device with improved data holding characteristic by using a negative voltage with high control responsiveness output from the above mentioned voltage generating circuit for driving the word line when holding data.
In short, the present invention is a voltage generating circuit generating a negative output voltage in accordance with a reference voltage and includes an sub-voltage generating circuit and a voltage converting circuit.
The voltage converting circuit is driven by a first voltage higher than the output voltage and a second negative voltage lower than the output voltage for generating an output voltage which follows the reference voltage.
The sub-voltage generating circuit supplies the second negative voltage and includes first to m-th sub-voltage converting circuits each driven by a corresponding first driving voltage which is equal to or lower than a ground voltage and equal to or higher than the second negative voltage and by a corresponding second driving voltage for generating a corresponding internal negative voltage.
The first sub-voltage converting circuit receives the ground voltage as the corresponding first driving voltage and a third positive voltage as the corresponding second driving voltage for generating and controlling a first internal negative voltage so as to maintain a difference between the first internal negative voltage and the third positive voltage within a prescribed value.
The i-th sub-voltage converting circuit (2xe2x89xa6ixe2x89xa6m) receives the (ixe2x88x921)th internal negative voltage generated by the (ixe2x88x921)th sub-voltage converting circuit as the corresponding first driving voltage and the (i+2)th positive voltage as the corresponding second driving voltage for generating and controlling an i-th internal negative voltage so as to maintain a difference between the i-th internal negative voltage and said (i+2)th positive voltage within the prescribed value.
The m-th sub-voltage converting circuit generates a second negative voltage as the m-th internal negative voltage.
According to another aspect of the present invention, a semiconductor memory device for inputting or outputting a storage data in accordance with an address signal is provided with a memory cell array, a word line, a row selecting means and a voltage generating circuit.
The memory cell array has a plurality of memory cells arranged in a matrix. The word line is arranged for every row of the memory cell. The row selecting means selectively activates the word line in accordance with the address signal. The voltage generating circuit includes: a voltage converting circuit driven by a first voltage higher than the an output voltage and a second negative voltage lower than the output voltage for generating an output voltage which follows a reference voltage; and an sub-voltage generating circuit generating the second negative voltage.
The sub-voltage generating circuit includes first to m-th sub-voltage converting circuits each driven by a corresponding first driving voltage which is equal to or lower than a ground voltage and equal to or higher than the second negative voltage and by a corresponding second driving voltage for generating a corresponding internal negative voltage.
The sub-voltage converting circuit receives a ground voltage as the corresponding first driving voltage and a third positive voltage as the corresponding second driving voltage for generating and controlling a first internal negative voltage so as to maintain a difference between the first internal negative voltage and the third positive voltage within a prescribed value.
The i-th sub-voltage converting circuit (2xe2x89xa6ixe2x89xa6m) receives the (ixe2x88x921)th internal negative voltage generated by the (ixe2x88x921)th sub-voltage converting circuit as the corresponding first driving voltage and the (i+2)th positive voltage as the corresponding second driving voltage for generating and controlling an i-th internal negative voltage so as to maintain a difference between the i-th internal negative voltage and said (i+2)th positive voltage within the prescribed value.
The m-th sub-voltage converting circuit generates a second negative voltage as the m-th internal negative voltage.
Therefore, a main advantage of the present invention is that a control responsiveness of the output voltage in the voltage converting circuit is enhanced while ensuring reliability of the transistor forming the sub-voltage converting circuit as the difference between the input voltage and the negative voltage to be output in the sub-voltage converting circuit is set at a value which is equal to or lower than the prescribed value and a negative voltage which is lower in steps is generated for obtaining the output voltage.
In addition, as the word line is driven when holding data of the memory cell by the voltage generating circuit capable of supplying a stable negative voltage, leakage current of the memory cell transistor is reduced and data holding characteristic is improved.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.